Tunnel transistors are currently considered promising candidates for future low-power high performance information processing applications. The proposed project TETTRA Towards Enhanced III-V Tunnel TRAnsistors is dedicated to the fabrication and characterization of III-V nano-wire tunnel field-effect transistors (FETs). III-V semiconductor heterostructure nano-wires, grown on Si substrates by means of the selective-area-epitaxy method, serve as basis for the tunnel FETs. The project concentrates on n-type tunnel FETs and furthermore focuses on one specific realization with regard to the choice of materials involved; i.e. n-type tunnel FETs consisting of a p-type GaSb source, an InxGa1-xAs channel, and an n-type InAs drain. This sequence of III-V materials is grown in the form of vertical hetero-structure nano-wires directly on silicon substrates, with InAs being in contact with the substrate and GaSb forming the nano-wire tip. The hetero-structure nano-wires are then processes into vertical, gate-all-around tunnel FETs. The fabrication of the nano-wire hetero-structure and the processing of the III-V nano-wire tunnel represent one of two main objectives of the project. Investigations on the growth of GaSb on InxGa1-xAs, on the p-doping of GaSb, and on metal contacts to GaSb are preceding the tunnel FET fabrication.
The second objective of the project comprises the electrical characterization of the nanowire-oxide interface properties and the electrical characterization of III-V tunnel FETs. For characterizing the nanowire-oxide interface properties two independent techniques will be employed: capacitance-voltage measurements and the charge-pumping technique. Both deliver the interface trap level density, Dit, and both have been demonstrated to be applicable to single nano-wire capacitors and FETs, respectively. Characterization is complemented by detailed investigations of the electrical properties of the III-V nano-wire tunnel FETs.