GRANTS FOR VERY ADVANCED NANOELECTRONIC COMPONENTS: DESIGN, ENGINEERING, TECHNOLOGY AND MANUFACTURABILITY
ICT-2011.3.1-a Beyond CMOS technology
- New switches and interconnects which offer scalability, performance and energy efficiency gains, operational reliability and room temperature operation with preferably CMOS process and architectural compatibility.- Advanced system integration technology...
ICT-2011.3.1-b Circuit-technology solutions
Addressing in a combined manner:- Architectures including energy efficiency, spin devices; silicon with molecular switches; ferromagnetic logic; heterogeneous and morphic system architectures.- Circuit design, methodology and tools addressing e.g....
ICT-2011.3.1-c Nano-manufacturing and Joint Equipment Assessment
Comprising the complete manufacturing supply chain for flexible and customised manufacturing of integrated nano and beyond-CMOS components:- Manufacturing approaches to Beyond-CMOS and advanced More-than-Moore', and to their integration with nanoCMOS...
ICT-2011.3.1-d Coordination and Support Actions
- Broker services to offer European researchers and SMEs access to training, to CAD tools and to advanced technologies, design kits and IP blocks for education, prototyping and small volume production.- Roadmaps; benchmarks; strategy papers; studies...
ICT-2013.3.1-b Advanced nanoelectronics manufacturing processes
This target outcomes includes: - More Moore IC Manufacturing: efficiency and productivity enhancement.- Manufacturing approaches to Beyond-CMOS and advanced More-than-Moore, and to their integration with nano-CMOS including 3D integration.
ICT-2013.3.1-d International Co-operation
This target outcome consist of one support action to develop a European strategy which addresses the challenges in manufacturing for 450 mm in dialogue with G450C and with the US, Korea, and Taiwan.
This objective addresses overcoming serious barriers, which are currently slowing down the expected evolution of CMOS, including the fundamental limits of devices and materials, system level limits, energy-efficiency, power density issues, design complexity issues, and cost.
It is in line with the ITRS roadmap.
It complements FET, and the more application driven and closer to market activities carried out under the ENIAC JU.
Take-up actions in nanoelectronics, including Europractice-type actions, are addressed under Objective 3.3
- Secured European industrial competence in advanced nanoelectronic technologies, and strengthened European capacity to manufacture nanoelectronic products.
- Improved performance at lower cost: improvements boosting
performance and functionality at all levels (device, circuit, system), and in particular in relation to a few critical parameters which drive integration and miniaturisation such as operating frequency, switching time, throughput, device or circuit complexity;
- Higher energy efficiency: reduction of device/circuit/system power consumption through improved energy per operation, efficiency of basic components, and control of leakage currents;
- Higher levels of integration and miniaturisation: improvement in component/functions per chip, cost per function, compactness, design productivity exploring new materials, architectures, and design - going beyond just an extension of known practices;
- Improved structuring: improvement in coordination of European research priorities and their industrial relevance, exploitation perspectives for Europe in terms of competitiveness and, jobs.